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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-04-30 16:43:05 +0200 |
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| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-05-03 17:33:26 +0200 |
| commit | 40ed073f893b1aaebbd7f2ef1259bab9a0cea46f (patch) | |
| tree | 9ac9d5169dd793173f945b935bda1450bcf8c0c3 /hw/core/machine.c | |
| parent | e88a856efd1d3c3ffa8e53da4831eff8da290808 (diff) | |
| download | focaccia-qemu-40ed073f893b1aaebbd7f2ef1259bab9a0cea46f.tar.gz focaccia-qemu-40ed073f893b1aaebbd7f2ef1259bab9a0cea46f.zip | |
target/sh4: Rename TCGv variables as manual for ADDV opcode
To easily compare with the SH4 manual, rename: REG(B11_8) -> Rn REG(B7_4) -> Rm t0 -> result Mention how overflow is calculated. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <20240430163125.77430-4-philmd@linaro.org>
Diffstat (limited to 'hw/core/machine.c')
0 files changed, 0 insertions, 0 deletions