summary refs log tree commit diff stats
path: root/hw/core/qdev-properties-system.c
diff options
context:
space:
mode:
authorMichael Clark <mjc@sifive.com>2018-03-06 10:33:31 +1300
committerMichael Clark <mjc@sifive.com>2018-05-06 10:39:38 +1200
commitb8643bd6084be1787a6dc8768a7a1983921fc945 (patch)
tree89d854a5e83b6aad4e7656604ccad89a29d169a5 /hw/core/qdev-properties-system.c
parent1d1ee55274860bfcc511d50d83c84394c2685ba8 (diff)
downloadfocaccia-qemu-b8643bd6084be1787a6dc8768a7a1983921fc945.tar.gz
focaccia-qemu-b8643bd6084be1787a6dc8768a7a1983921fc945.zip
RISC-V: No traps on writes to misa,minstret,mcycle
These fields are marked WARL (Write Any Values, Reads
Legal Values) in the RISC-V Privileged Architecture
Specification so instead of raising exceptions,
illegal writes are silently dropped.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Diffstat (limited to 'hw/core/qdev-properties-system.c')
0 files changed, 0 insertions, 0 deletions