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authorTaylor Simpson <tsimpson@quicinc.com>2021-10-04 19:12:31 -0500
committerTaylor Simpson <tsimpson@quicinc.com>2021-10-28 22:22:49 -0500
commitb9dd6ff91d29b9e38afd7facf1d683f34bd1ec10 (patch)
tree3545ca5315862dad7b2d90b681cc3f016bc71f1f /hw/core/qdev.c
parentf448397a512189e726f5e8026c89ce7fc4392377 (diff)
downloadfocaccia-qemu-b9dd6ff91d29b9e38afd7facf1d683f34bd1ec10.tar.gz
focaccia-qemu-b9dd6ff91d29b9e38afd7facf1d683f34bd1ec10.zip
Hexagon (target/hexagon) put writes to USR into temp until commit
Change SET_USR_FIELD to write to hex_new_value[HEX_REG_USR] instead
of hex_gpr[HEX_REG_USR].

Then, we need code to mark the instructions that can set implicitly
set USR
- Macros added to hex_common.py
- A_FPOP added in translate.c

Test case added in tests/tcg/hexagon/overflow.c

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Diffstat (limited to 'hw/core/qdev.c')
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