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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-02-12 16:43:32 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-02-20 14:20:29 +0000 |
| commit | 2bf8bdcbb4510f206b3d0203c9bb8fb433387a90 (patch) | |
| tree | 7e3db217b2fcd76e2967c724800b752159831bdc /hw/cpu/a9mpcore.c | |
| parent | e2e5266c4555ed24a4727c9ce6e34eb5213a9ab6 (diff) | |
| download | focaccia-qemu-2bf8bdcbb4510f206b3d0203c9bb8fb433387a90.tar.gz focaccia-qemu-2bf8bdcbb4510f206b3d0203c9bb8fb433387a90.zip | |
hw/arm/highbank: Specify explicitly the GIC has 128 external IRQs
When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"), and Cortex-15MP to 128 (see commit 528622421eb
"hw/cpu/a15mpcore: Correct default value for num-irq").
The Caldexa Highbank board however expects a fixed set of 128
interrupts (see the fixed IRQ length when this board was added in
commit 2488514cef2 ("arm: SoC model for Calxeda Highbank"). Add the
GIC_EXT_IRQS definition (with a comment) to make that explicit.
Except explicitly setting a property value to its same implicit
value, there is no logical change intended.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250212154333.28644-8-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/cpu/a9mpcore.c')
0 files changed, 0 insertions, 0 deletions