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| author | Jinjie Ruan <ruanjinjie@huawei.com> | 2024-04-19 14:33:05 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-04-25 10:21:05 +0100 |
| commit | d89daa893f51280652032640d77a8bc1dea95bdd (patch) | |
| tree | d3bac7181c238c7f9a7269a2deb118be0d70fca7 /hw/intc/apic_common.c | |
| parent | d2c0c6aab6c6748726149c37159a75751ec6ac92 (diff) | |
| download | focaccia-qemu-d89daa893f51280652032640d77a8bc1dea95bdd.tar.gz focaccia-qemu-d89daa893f51280652032640d77a8bc1dea95bdd.zip | |
hw/intc/arm_gicv3: Implement NMI interrupt priority
If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI priority is higher than 0x80, otherwise it is higher than 0x0. And save the interrupt non-maskable property in hppi.nmi to deliver NMI exception. Since both GICR and GICD can deliver NMI, it is both necessary to check whether the pending irq is NMI in gicv3_redist_update_noirqset and gicv3_update_noirqset. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-21-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/apic_common.c')
0 files changed, 0 insertions, 0 deletions