diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2016-06-17 15:23:47 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-06-17 15:23:51 +0100 |
| commit | 359fbe65e01e13f582d3b9103e7c3ec5ac367a18 (patch) | |
| tree | 5dc875f829bcdb3e3aab7480542a0ebe9e41b98b /hw/intc/arm_gicv3.c | |
| parent | c84428b33fc2d88f17c3f599a9e5d17ae23422c1 (diff) | |
| download | focaccia-qemu-359fbe65e01e13f582d3b9103e7c3ec5ac367a18.tar.gz focaccia-qemu-359fbe65e01e13f582d3b9103e7c3ec5ac367a18.zip | |
hw/intc/arm_gicv3: Implement GICv3 CPU interface registers
Implement the CPU interface registers for the GICv3; these are CPU system registers, not MMIO registers. This commit implements all the registers which are simple accessors for GIC state, but not those which act as interfaces for acknowledging, dismissing or generating interrupts. (Those will be added in a later commit.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-16-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc/arm_gicv3.c')
| -rw-r--r-- | hw/intc/arm_gicv3.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index 65ebca2e0a..8a6c647219 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -369,6 +369,8 @@ static void arm_gic_realize(DeviceState *dev, Error **errp) } gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops); + + gicv3_init_cpuif(s); } static void arm_gicv3_class_init(ObjectClass *klass, void *data) |