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| author | Vijaya Kumar K <Vijaya.Kumar@cavium.com> | 2017-02-23 17:21:11 +0530 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-02-28 17:10:00 +0000 |
| commit | 367b9f527becdd20ddf116e17a3c0c2bbc486920 (patch) | |
| tree | 90250fff99eef1a1929ebb45c8fe6ed6616f63d9 /hw/intc/arm_gicv3_common.c | |
| parent | 6692aac41119906409dfa634ecbe3ef1634b5e5c (diff) | |
| download | focaccia-qemu-367b9f527becdd20ddf116e17a3c0c2bbc486920.tar.gz focaccia-qemu-367b9f527becdd20ddf116e17a3c0c2bbc486920.zip | |
hw/intc/arm_gicv3_kvm: Implement get/put functions
This actually implements pre_save and post_load methods for in-kernel vGICv3. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com> Message-id: 1487850673-26455-4-git-send-email-vijay.kilari@gmail.com [PMM: * use decimal, not 0bnnn * fixed typo in names of ICC_APR0R_EL1 and ICC_AP1R_EL1 * completely rearranged the get and put functions to read and write the state in a natural order, rather than mixing distributor and redistributor state together] Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com> [Vijay: * Update macro KVM_VGIC_ATTR * Use 32 bit access for gicd and gicr * GICD_IROUTER, GICD_TYPER, GICR_PROPBASER and GICR_PENDBASER reg access are changed from 64-bit to 32-bit access * Add ICC_SRE_EL1 save and restore * Dropped translate_fn mechanism and coded functions to handle save and restore of edge_trigger and priority * Number of APnR register saved/restored based on number of priority bits supported] Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/arm_gicv3_common.c')
0 files changed, 0 insertions, 0 deletions