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| author | Peter Maydell <peter.maydell@linaro.org> | 2024-03-31 16:42:48 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-03-31 16:42:48 +0100 |
| commit | c919bc65c54433420eecf8dc918ed6bcfeab40bf (patch) | |
| tree | 3e954be807b2c797915b52f6c622380fea4d4606 /hw/intc/arm_gicv3_common.c | |
| parent | b9dbf6f9bf533564f6a4277d03906fcd32bb0245 (diff) | |
| parent | 4a3aa11e1fb25c28c24a43fd2835c429b00a463d (diff) | |
| download | focaccia-qemu-c919bc65c54433420eecf8dc918ed6bcfeab40bf.tar.gz focaccia-qemu-c919bc65c54433420eecf8dc918ed6bcfeab40bf.zip | |
Merge tag 'pull-pa-20240329' of https://gitlab.com/rth7680/qemu into staging
target/hppa: Fix BE,L set of sr0 target/hppa: Fix B,GATE for wide mode target/hppa: Mark interval timer write as io target/hppa: Fix EIRR, EIEM versus icount target/hppa: Fix DCOR reconstruction of carry bits target/hppa: Fix unit carry conditions target/hppa: Fix overflow computation for shladd target/hppa: Add diag instructions to set/restore shadow registers target/hppa: Clear psw_n for BE on use_nullify_skip path # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmYHQPEdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/lpwf+PRmKNguclUYZ5Pub # kVxeylyTGdiYieDfv4RxSnkQbmfiJdwhr+lRUiiA/AfK2IFMTC56Wn0URAdvpFxG # MuI9r7t8Z640KwVnF9GTau0JagU/GXYorYdO7WY/PMvrgjeRukjMqb0Sgnoknlqw # LuPUu6+Z+zMMNLT69WNfbcYIqdHcb2iP5Tr3yWGRKywu8+zM9q/fL7GEi+5GEB6Y # bljjv03hpzKPyZg6UCwQzoeDnIfUpefrghkwzenPKmoWzuLSohmG+Q7Cnp4WiGMg # 3HX7+LVCXXW4OOHu0syf3M/cG6zGfH7kBTvq4CNKjNeeqz/g2qwNTPO1xfOr7f5w # zsUf/Q== # =fcSC # -----END PGP SIGNATURE----- # gpg: Signature made Fri 29 Mar 2024 22:30:09 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-pa-20240329' of https://gitlab.com/rth7680/qemu: target/hppa: Clear psw_n for BE on use_nullify_skip path target/hppa: Add diag instructions to set/restore shadow registers target/hppa: Move diag argument handling to decodetree target/hppa: Generate getshadowregs inline target/hppa: Fix overflow computation for shladd target/hppa: Replace c with uv in do_cond target/hppa: Squash d for pa1.x during decode target/hppa: Fix unit carry conditions target/hppa: Optimize UADDCM with no condition target/hppa: Fix DCOR reconstruction of carry bits target/hppa: Use gva_offset_mask() everywhere target/hppa: Fix EIRR, EIEM versus icount target/hppa: Tidy read of interval timer target/hppa: Mark interval timer write as io target/hppa: Fix ADD/SUB trap on overflow for narrow mode target/hppa: Handle unit conditions for wide mode target/hppa: Fix B,GATE for wide mode target/hppa: Fix BE,L set of sr0 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/arm_gicv3_common.c')
0 files changed, 0 insertions, 0 deletions