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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-05-05 19:39:48 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-05-19 16:19:01 +0100 |
| commit | 4a0b47c8150d3ac0a90f470191d64a3b199e6269 (patch) | |
| tree | b9e01f502b42b3b68601745884843d12a0085f37 /hw/intc/arm_gicv3_cpuif.c | |
| parent | 9f225e607f215003de1e4157255bb0199adff9aa (diff) | |
| download | focaccia-qemu-4a0b47c8150d3ac0a90f470191d64a3b199e6269.tar.gz focaccia-qemu-4a0b47c8150d3ac0a90f470191d64a3b199e6269.zip | |
target/arm: Factor out FWB=0 specific part of combine_cacheattrs()
Factor out the part of combine_cacheattrs() that is specific to handling HCR_EL2.FWB == 0. This is the part where we combine the memory type and cacheability attributes. The "force Outer Shareable for Device or Normal Inner-NC Outer-NC" logic remains in combine_cacheattrs() because it holds regardless (this is the equivalent of the pseudocode EffectiveShareability() function). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220505183950.2781801-3-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc/arm_gicv3_cpuif.c')
0 files changed, 0 insertions, 0 deletions