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authorGustavo Romero <gustavo.romero@linaro.org>2025-08-26 11:21:28 +0100
committerPeter Maydell <peter.maydell@linaro.org>2025-08-30 16:37:22 +0100
commit8a60ffe9a8f46ed514656eb4a40d1386c439daf8 (patch)
tree1996024bd522336c13fc8b89f0e95eac9e0032b5 /hw/intc/arm_gicv3_cpuif.c
parent84249d026bc3878c196ecd3e8558609ba9260eb6 (diff)
downloadfocaccia-qemu-8a60ffe9a8f46ed514656eb4a40d1386c439daf8.tar.gz
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target/arm: Implement FEAT_SCTLR2 and enable with -cpu max
Add FEAT_SCTLR2, which introduces the SCTLR2_EL1, SCTLR2_EL2, and
SCTLR2_EL3 registers. These registers are extensions of the SCTLR_ELx
ones.

Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250727074202.83141-4-richard.henderson@linaro.org
Message-ID: <20250711140828.1714666-4-gustavo.romero@linaro.org>
[rth: Remove FEAT_MEC code; handle SCR and HCRX enable bits.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/arm_gicv3_cpuif.c')
0 files changed, 0 insertions, 0 deletions