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| author | Alexandra Diupina <adiupina@astralinux.ru> | 2024-10-14 17:05:50 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-10-15 11:29:45 +0100 |
| commit | e0c0ea6eca4f210a52b9742817586cc97b1ee434 (patch) | |
| tree | 5624cf762fdde5e984a3b6942736e3272d98ef57 /hw/intc/arm_gicv3_cpuif.c | |
| parent | 950dff9aa4dc1f287ea001e7d2689dcc76a7f1c4 (diff) | |
| download | focaccia-qemu-e0c0ea6eca4f210a52b9742817586cc97b1ee434.tar.gz focaccia-qemu-e0c0ea6eca4f210a52b9742817586cc97b1ee434.zip | |
hw/intc/arm_gicv3: Add cast to match the documentation
The result of 1 << regbit with regbit==31 has a 1 in the 32nd bit.
When cast to uint64_t (for further bitwise OR), the 32 most
significant bits will be filled with 1s. However, the documentation
states that the upper 32 bits of ICH_AP[0/1]R<n>_EL2 are reserved.
Add an explicit cast to match the documentation.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Cc: qemu-stable@nongnu.org
Fixes: d2c0c6aab6 ("hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read()")
Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/arm_gicv3_cpuif.c')
| -rw-r--r-- | hw/intc/arm_gicv3_cpuif.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index bdb13b00e9..ebad7aaea1 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -781,7 +781,7 @@ static void icv_activate_irq(GICv3CPUState *cs, int idx, int grp) if (nmi) { cs->ich_apr[grp][regno] |= ICV_AP1R_EL1_NMI; } else { - cs->ich_apr[grp][regno] |= (1 << regbit); + cs->ich_apr[grp][regno] |= (1U << regbit); } } |