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| author | Peter Maydell <peter.maydell@linaro.org> | 2024-04-19 14:36:00 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-04-25 10:21:05 +0100 |
| commit | 28cca59c469b16f1352e784b566fd36ace2be4b4 (patch) | |
| tree | 981d70617b07e41128872ef2f5db5ac084b319b5 /hw/intc/gicv3_internal.h | |
| parent | 44ed1e4b9a4df256bb56487ae5150b6807536703 (diff) | |
| download | focaccia-qemu-28cca59c469b16f1352e784b566fd36ace2be4b4.tar.gz focaccia-qemu-28cca59c469b16f1352e784b566fd36ace2be4b4.zip | |
hw/intc/arm_gicv3: Add NMI handling CPU interface registers
Add the NMIAR CPU interface registers which deal with acknowledging NMI. When introduce NMI interrupt, there are some updates to the semantics for the register ICC_IAR1_EL1 and ICC_HPPIR1_EL1. For ICC_IAR1_EL1 register, it should return 1022 if the intid has non-maskable property. And for ICC_NMIAR1_EL1 register, it should return 1023 if the intid do not have non-maskable property. Howerever, these are not necessary for ICC_HPPIR1_EL1 register. And the APR and RPR has NMI bits which should be handled correctly. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [PMM: Separate out whether cpuif supports NMI from whether the GIC proper (IRI) supports NMI] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-19-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/gicv3_internal.h')
| -rw-r--r-- | hw/intc/gicv3_internal.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 8d793243f4..81200eb90e 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -194,6 +194,10 @@ FIELD(GICR_VPENDBASER, VALID, 63, 1) #define ICC_CTLR_EL3_A3V (1U << 15) #define ICC_CTLR_EL3_NDS (1U << 17) +#define ICC_AP1R_EL1_NMI (1ULL << 63) +#define ICC_RPR_EL1_NSNMI (1ULL << 62) +#define ICC_RPR_EL1_NMI (1ULL << 63) + #define ICH_VMCR_EL2_VENG0_SHIFT 0 #define ICH_VMCR_EL2_VENG0 (1U << ICH_VMCR_EL2_VENG0_SHIFT) #define ICH_VMCR_EL2_VENG1_SHIFT 1 @@ -511,6 +515,7 @@ FIELD(VTE, RDBASE, 42, RDBASE_PROCNUM_LENGTH) /* Special interrupt IDs */ #define INTID_SECURE 1020 #define INTID_NONSECURE 1021 +#define INTID_NMI 1022 #define INTID_SPURIOUS 1023 /* Functions internal to the emulated GICv3 */ |