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| author | Jinjie Ruan <ruanjinjie@huawei.com> | 2024-04-19 14:33:03 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-04-25 10:21:05 +0100 |
| commit | 44ed1e4b9a4df256bb56487ae5150b6807536703 (patch) | |
| tree | c4e00d1f43dd65a0abbd14061c830fdecfc673bc /hw/intc/gicv3_internal.h | |
| parent | 7c79d98d2e4de5b8c919002e6ead6bae7f46003d (diff) | |
| download | focaccia-qemu-44ed1e4b9a4df256bb56487ae5150b6807536703.tar.gz focaccia-qemu-44ed1e4b9a4df256bb56487ae5150b6807536703.zip | |
hw/intc/arm_gicv3: Implement GICD_INMIR
Add GICD_INMIR, GICD_INMIRnE register and support access GICD_INMIR0. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-18-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/gicv3_internal.h')
| -rw-r--r-- | hw/intc/gicv3_internal.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 21697ecf39..8d793243f4 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -52,6 +52,8 @@ #define GICD_SGIR 0x0F00 #define GICD_CPENDSGIR 0x0F10 #define GICD_SPENDSGIR 0x0F20 +#define GICD_INMIR 0x0F80 +#define GICD_INMIRnE 0x3B00 #define GICD_IROUTER 0x6000 #define GICD_IDREGS 0xFFD0 |