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authorPeter Maydell <peter.maydell@linaro.org>2022-04-08 15:15:31 +0100
committerPeter Maydell <peter.maydell@linaro.org>2022-04-22 14:44:52 +0100
commitae3b3ba15c73320f75c121b08266a25a9e5d4edb (patch)
tree1b247f393eee5c741a56072fae2f6c10196884e5 /hw/intc/gicv3_internal.h
parentc6dd2f9950cb59f7a02d57dcefef4d982efc6c7e (diff)
downloadfocaccia-qemu-ae3b3ba15c73320f75c121b08266a25a9e5d4edb.tar.gz
focaccia-qemu-ae3b3ba15c73320f75c121b08266a25a9e5d4edb.zip
hw/intc/arm_gicv3: Implement GICv4's new redistributor frame
The GICv4 extends the redistributor register map -- where GICv3
had two 64KB frames per CPU, GICv4 has four frames. Add support
for the extra frame by using a new gicv3_redist_size() function
in the places in the GIC implementation which currently use
a fixed constant size for the redistributor register block.
(Until we implement the extra registers they will RAZ/WI.)

Any board that wants to use a GICv4 will need to also adjust
to handle the different sized redistributor register block;
that will be done separately.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-23-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc/gicv3_internal.h')
-rw-r--r--hw/intc/gicv3_internal.h21
1 files changed, 21 insertions, 0 deletions
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
index a46d1378a9..9fff1cd52a 100644
--- a/hw/intc/gicv3_internal.h
+++ b/hw/intc/gicv3_internal.h
@@ -490,6 +490,27 @@ FIELD(VTE, RDBASE, 42, RDBASE_PROCNUM_LENGTH)
 /* Functions internal to the emulated GICv3 */
 
 /**
+ * gicv3_redist_size:
+ * @s: GICv3State
+ *
+ * Return the size of the redistributor register frame in bytes
+ * (which depends on what GIC version this is)
+ */
+static inline int gicv3_redist_size(GICv3State *s)
+{
+    /*
+     * Redistributor size is controlled by the redistributor GICR_TYPER.VLPIS.
+     * It's the same for every redistributor in the GIC, so arbitrarily
+     * use the register field in the first one.
+     */
+    if (s->cpu[0].gicr_typer & GICR_TYPER_VLPIS) {
+        return GICV4_REDIST_SIZE;
+    } else {
+        return GICV3_REDIST_SIZE;
+    }
+}
+
+/**
  * gicv3_intid_is_special:
  * @intid: interrupt ID
  *