diff options
| author | Cédric Le Goater <clg@kaod.org> | 2019-10-22 18:38:10 +0200 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2019-10-24 13:33:45 +1100 |
| commit | d49e8a9b46e4594223806ae622af462ff7bfa158 (patch) | |
| tree | 3e04bc8cdde19b9191801a57a9d2066de213348d /hw/intc/imx_gpcv2.c | |
| parent | aa5ac64b2394712b6269d0b15ba06c9c564dee92 (diff) | |
| download | focaccia-qemu-d49e8a9b46e4594223806ae622af462ff7bfa158.tar.gz focaccia-qemu-d49e8a9b46e4594223806ae622af462ff7bfa158.zip | |
ppc: Reset the interrupt presenter from the CPU reset handler
On the sPAPR machine and PowerNV machine, the interrupt presenters are created by a machine handler at the core level and are reset independently. This is not consistent and it raises issues when it comes to handle hot-plugged CPUs. In that case, the presenters are not reset. This is less of an issue in XICS, although a zero MFFR could be a concern, but in XIVE, the OS CAM line is not set and this breaks the presenting algorithm. The current code has workarounds which need a global cleanup. Extend the sPAPR IRQ backend and the PowerNV Chip class with a new cpu_intc_reset() handler called by the CPU reset handler and remove the XiveTCTX reset handler which is now redundant. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191022163812.330-6-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw/intc/imx_gpcv2.c')
0 files changed, 0 insertions, 0 deletions