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| author | demin.han <demin.han@starfivetech.com> | 2024-02-26 01:41:14 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-03-08 20:48:03 +1000 |
| commit | 938dd05ea1f3a9e3c713b1d73dc2992d62efb830 (patch) | |
| tree | 51534578d6023330daf4fc353dc8e78849815f4e /hw/intc/riscv_aplic.c | |
| parent | a506c4289dd05b3134a1b6eb0b506eaee81e224d (diff) | |
| download | focaccia-qemu-938dd05ea1f3a9e3c713b1d73dc2992d62efb830.tar.gz focaccia-qemu-938dd05ea1f3a9e3c713b1d73dc2992d62efb830.zip | |
target/riscv: Fix shift count overflow
The result of (8 - 3 - vlmul) is negative when vlmul >= 6, and results in wrong vill. Signed-off-by: demin.han <demin.han@starfivetech.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240225174114.5298-1-demin.han@starfivetech.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/intc/riscv_aplic.c')
0 files changed, 0 insertions, 0 deletions