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| author | Yong-Xuan Wang <yongxuan.wang@sifive.com> | 2025-02-24 10:57:18 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-03-04 15:42:54 +1000 |
| commit | afd4f4aa7f605caf8efa2f3c590e1f2572f1ea50 (patch) | |
| tree | 0f8f88401b1c922835d993955064fb20fc83007f /hw/intc/riscv_aplic.c | |
| parent | 1887cf2368189087fdf977fb8d09b5ad47cc7aea (diff) | |
| download | focaccia-qemu-afd4f4aa7f605caf8efa2f3c590e1f2572f1ea50.tar.gz focaccia-qemu-afd4f4aa7f605caf8efa2f3c590e1f2572f1ea50.zip | |
hw/intc/imsic: refine the IMSIC realize
When the IMSIC is emulated in the kernel, the GPIO output lines to CPUs and aia_ireg_rmw_fn setting can be remove. In this case the IMSIC trigger CPU interrupts by KVM APIs, and the RMW of IREG is handled in kernel. This patch also move the code that claim the CPU interrupts to the beginning of IMSIC realization. This can avoid the unnecessary resource allocation before checking failed. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250224025722.3999-2-yongxuan.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/intc/riscv_aplic.c')
0 files changed, 0 insertions, 0 deletions