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authorStefan Hajnoczi <stefanha@redhat.com>2025-03-23 11:03:33 -0400
committerStefan Hajnoczi <stefanha@redhat.com>2025-03-23 11:03:34 -0400
commit3907add7a6016401e58e8dbe5b2ddfa06cd1f66a (patch)
tree9935d6992f8e48a03f2e160bfda35058c286ea72 /hw/intc/xive.c
parent5eb0849562c9b6988b620493dbea6421e31bfc33 (diff)
parent73c0c904fc99e2ceecbbded84ec76d40d3f2daae (diff)
downloadfocaccia-qemu-3907add7a6016401e58e8dbe5b2ddfa06cd1f66a.tar.gz
focaccia-qemu-3907add7a6016401e58e8dbe5b2ddfa06cd1f66a.zip
Merge tag 'pull-ppc-for-10.0-2-20250321' of https://gitlab.com/npiggin/qemu into staging
* Fix a KVM SMP guest hang. This is not completely trivial, but just
  small enough to merge it. If this causes any more problems, we can
  revert it and the timebase patch which exposed the underlying issue
  for release.
* Fix a bunch of Coverity issues reported introduced in ppc, mostly in
  powernv code.
* Fix a NetBSD boot bug on mac99 caused by VSX/VMX decodetree rewrite.
* Fix the default CPU selection for older spapr machines.

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* tag 'pull-ppc-for-10.0-2-20250321' of https://gitlab.com/npiggin/qemu:
  target/ppc: Fix e200 duplicate SPRs
  target/ppc: Fix facility interrupt checks for VSX
  ppc/spapr: fix default cpu for pre-9.0 machines.
  ppc/amigaone: Constify default_env
  ppc/amigaone: Check blk_pwrite return value
  ppc/pnv: Fix system symbols in HOMER structure definitions
  ppc/pnv: Move the PNOR LPC address into struct PnvPnor
  ppc/spapr: Fix possible pa_features memory overflow
  ppc/xive2: Fix logical / bitwise comparison typo
  pnv/xive: Fix possible undefined shift error in group size calculation
  ppc/xive: Fix typo in crowd block level calculation
  ppc/spapr: Fix RTAS stopped state

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Diffstat (limited to 'hw/intc/xive.c')
-rw-r--r--hw/intc/xive.c29
1 files changed, 25 insertions, 4 deletions
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index c77df2c1f8..3eb28c2265 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1662,12 +1662,20 @@ uint32_t xive_get_vpgroup_size(uint32_t nvp_index)
      * (starting with the least significant bits) in the NVP index
      * gives the size of the group.
      */
-    return 1 << (ctz32(~nvp_index) + 1);
+    int first_zero = cto32(nvp_index);
+    if (first_zero >= 31) {
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid group index 0x%08x",
+                                       nvp_index);
+        return 0;
+    }
+
+    return 1U << (first_zero + 1);
 }
 
 static uint8_t xive_get_group_level(bool crowd, bool ignore,
                                     uint32_t nvp_blk, uint32_t nvp_index)
 {
+    int first_zero;
     uint8_t level;
 
     if (!ignore) {
@@ -1675,18 +1683,31 @@ static uint8_t xive_get_group_level(bool crowd, bool ignore,
         return 0;
     }
 
-    level = (ctz32(~nvp_index) + 1) & 0b1111;
+    first_zero = cto32(nvp_index);
+    if (first_zero >= 31) {
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid group index 0x%08x",
+                                       nvp_index);
+        return 0;
+    }
+
+    level = (first_zero + 1) & 0b1111;
     if (crowd) {
         uint32_t blk;
 
         /* crowd level is bit position of first 0 from the right in nvp_blk */
-        blk = ctz32(~nvp_blk) + 1;
+        first_zero = cto32(nvp_blk);
+        if (first_zero >= 31) {
+            qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid crowd block 0x%08x",
+                                           nvp_blk);
+            return 0;
+        }
+        blk = first_zero + 1;
 
         /*
          * Supported crowd sizes are 2^1, 2^2, and 2^4. 2^3 is not supported.
          * HW will encode level 4 as the value 3.  See xive2_pgofnext().
          */
-        switch (level) {
+        switch (blk) {
         case 1:
         case 2:
             break;