Merge tag 'pull-ppc-for-20250928-20250929' of https://gitlab.com/harshpb/qemu into staging

ppc queue for 20250928

* Support for PowerNV11 and PPE42 CPU/Machines.
* Deprecation of Power8E and Power8NVL
* Decodetree patches for some floating-point instructions
* Minor bug fixes, improvements in ppc/spapr/xive/xics.

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# Primary key fingerprint: 6B81 0CD6 D2BE 10F3 883D  2142 4544 E994 F9D6 8FBB

* tag 'pull-ppc-for-20250928-20250929' of https://gitlab.com/harshpb/qemu: (27 commits)
  target/ppc: use MAKE_64BIT_MASK for mcrfs exception clear mask
  target/ppc: Deprecate Power8E and Power8NVL
  target/ppc: Introduce macro for deprecating PowerPC CPUs
  target/ppc: Move remaining floating-point move instructions to decodetree.
  target/ppc: Move floating-point move instructions to decodetree.
  target/ppc: Move floating-point compare instructions to decodetree.
  target/ppc: Move floating-point rounding and conversion instructions to decodetree.
  ppc/xive2: Fix integer overflow warning in xive2_redistribute()
  ppc/spapr: init lrdr-capapcity phys with ram size if maxmem not provided
  hw/intc/xics: Add missing call to register vmstate_icp_server
  tests/functional: Add test for IBM PPE42 instructions
  hw/ppc: Add a test machine for the IBM PPE42 CPU
  hw/ppc: Support for an IBM PPE42 CPU decrementer
  target/ppc: Add IBM PPE42 special instructions
  target/ppc: Support for IBM PPE42 MMU
  target/ppc: Add IBM PPE42 exception model
  target/ppc: IBM PPE42 exception flags and regs
  target/ppc: Add IBM PPE42 family of processors
  target/ppc: IBM PPE42 general regs and flags
  tests/powernv: Add PowerNV test for Power11
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

1 files changed, 31 insertions, 14 deletions

diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index ee5fa26178..fbb3b7975e 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -95,6 +95,35 @@ static void xive2_nvgc_set_backlog(Xive2Nvgc *nvgc, uint8_t priority,
     }
 }
 
+static uint32_t xive2_nvgc_get_idx(uint32_t nvp_idx, uint8_t group)
+{
+    uint32_t nvgc_idx;
+
+    if (group > 0) {
+        nvgc_idx = (nvp_idx & (0xffffffffULL << group)) |
+                   ((1 << (group - 1)) - 1);
+    } else {
+        nvgc_idx = nvp_idx;
+    }
+
+    return nvgc_idx;
+}
+
+static uint8_t xive2_nvgc_get_blk(uint8_t nvp_blk, uint8_t crowd)
+{
+    uint8_t nvgc_blk;
+
+    if (crowd > 0) {
+        crowd = (crowd == 3) ? 4 : crowd;
+        nvgc_blk = (nvp_blk & (0xffffffffULL << crowd)) |
+                   ((1 << (crowd - 1)) - 1);
+    } else {
+        nvgc_blk = nvp_blk;
+    }
+
+    return nvgc_blk;
+}
+
 uint64_t xive2_presenter_nvgc_backlog_op(XivePresenter *xptr,
                                          bool crowd,
                                          uint8_t blk, uint32_t idx,
@@ -638,20 +667,8 @@ static void xive2_redistribute(Xive2Router *xrtr, XiveTCTX *tctx, uint8_t ring)
 
     trace_xive_redistribute(tctx->cs->cpu_index, ring, nvp_blk, nvp_idx);
     /* convert crowd/group to blk/idx */
-    if (group > 0) {
-        nvgc_idx = (nvp_idx & (0xffffffff << group)) |
-                   ((1 << (group - 1)) - 1);
-    } else {
-        nvgc_idx = nvp_idx;
-    }
-
-    if (crowd > 0) {
-        crowd = (crowd == 3) ? 4 : crowd;
-        nvgc_blk = (nvp_blk & (0xffffffff << crowd)) |
-                   ((1 << (crowd - 1)) - 1);
-    } else {
-        nvgc_blk = nvp_blk;
-    }
+    nvgc_idx = xive2_nvgc_get_idx(nvp_idx, group);
+    nvgc_blk = xive2_nvgc_get_blk(nvp_blk, crowd);
 
     /* Use blk/idx to retrieve the NVGC */
     if (xive2_router_get_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, &nvgc)) {