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| author | Bibo Mao <maobibo@loongson.cn> | 2025-05-07 10:31:38 +0800 |
|---|---|---|
| committer | Song Gao <gaosong@loongson.cn> | 2025-05-14 15:46:08 +0800 |
| commit | 53339a8120d9be6a448f29dd1138bab2fa15e34d (patch) | |
| tree | 5ed505386f4d9253315ff86f06322c1c97d2ba81 /hw/intc | |
| parent | ab3ab67348b1e34630272b05f9f7f187fd6a1f8f (diff) | |
| download | focaccia-qemu-53339a8120d9be6a448f29dd1138bab2fa15e34d.tar.gz focaccia-qemu-53339a8120d9be6a448f29dd1138bab2fa15e34d.zip | |
hw/intc/loongarch_pch: Discard write operation with ISR register
With the latest 7A1000 user manual, interrupt status register ISR is read only. Here discard write operation with ISR register. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023148.1877287-7-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/loongarch_pch_pic.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c index 9b64bf938f..e6fcf645eb 100644 --- a/hw/intc/loongarch_pch_pic.c +++ b/hw/intc/loongarch_pch_pic.c @@ -234,12 +234,6 @@ static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr, trace_loongarch_pch_pic_high_writew(size, addr, data); switch (addr) { - case PCH_PIC_INT_STATUS: - s->intisr = get_writew_val(s->intisr, data, 0); - break; - case PCH_PIC_INT_STATUS + 4: - s->intisr = get_writew_val(s->intisr, data, 1); - break; case PCH_PIC_INT_POL: s->int_polarity = get_writew_val(s->int_polarity, data, 0); break; |