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| author | Nicholas Piggin <npiggin@gmail.com> | 2025-05-12 13:10:54 +1000 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-07-21 08:03:53 +0200 |
| commit | 6936d2f561759c00993217a424ddeb1554c5f1ff (patch) | |
| tree | 85fb2158f14f87624bb2acba50b4fd0950f58989 /hw/intc | |
| parent | ba127a1e48d34f6c805000dc881e240fc4f2bd1d (diff) | |
| download | focaccia-qemu-6936d2f561759c00993217a424ddeb1554c5f1ff.tar.gz focaccia-qemu-6936d2f561759c00993217a424ddeb1554c5f1ff.zip | |
ppc/xive2: redistribute group interrupts on context push
When pushing a context, any presented group interrupt should be redistributed before processing pending interrupts to present highest priority. This can occur when pushing the POOL ring when the valid PHYS ring has a group interrupt presented, because they share signal registers. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-46-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/xive2.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 4244e1d02b..23eb85bb86 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -945,8 +945,9 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx, uint8_t nvp_blk, uint32_t nvp_idx, bool do_restore) { + uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring); uint8_t *regs = &tctx->regs[ring]; - uint8_t ipb; + uint8_t ipb, nsr = sig_regs[TM_NSR]; Xive2Nvp nvp; /* @@ -978,6 +979,11 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx, /* IPB bits in the backlog are merged with the TIMA IPB bits */ regs[TM_IPB] |= ipb; + if (xive_nsr_indicates_group_exception(ring, nsr)) { + /* redistribute precluded active grp interrupt */ + g_assert(ring == TM_QW2_HV_POOL); /* PHYS ring has the grp interrupt */ + xive2_redistribute(xrtr, tctx, xive_nsr_exception_ring(ring, nsr)); + } xive2_tctx_process_pending(tctx, ring == TM_QW2_HV_POOL ? TM_QW3_HV_PHYS : ring); } |