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| author | Michael Davidsaver <mdavidsaver@gmail.com> | 2017-01-27 15:20:24 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-01-27 15:29:08 +0000 |
| commit | bdd04fc76a78d61ae0f0e93ce345f9cf2e49a9a8 (patch) | |
| tree | 706716bfbd2a5a52d4243222b859ad828ab745ab /hw/intc | |
| parent | 7517748e3f71a3099e57915fba95c4c308e6d842 (diff) | |
| download | focaccia-qemu-bdd04fc76a78d61ae0f0e93ce345f9cf2e49a9a8.tar.gz focaccia-qemu-bdd04fc76a78d61ae0f0e93ce345f9cf2e49a9a8.zip | |
armv7m: Honour CCR.USERSETMPEND
The CCR.USERSETMPEND bit has to be set to permit unprivileged code to write to the Software Triggered Interrupt register; honour this bit rather than letting any code write to the register. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-9-git-send-email-peter.maydell@linaro.org [PMM: Tweak commit message, comment, phrasing of condition] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/armv7m_nvic.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 60e72d7395..fe5c303de9 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -409,7 +409,10 @@ static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value) "NVIC: Aux fault status registers unimplemented\n"); break; case 0xf00: /* Software Triggered Interrupt Register */ - if ((value & 0x1ff) < s->num_irq) { + /* user mode can only write to STIR if CCR.USERSETMPEND permits it */ + if ((value & 0x1ff) < s->num_irq && + (arm_current_el(&cpu->env) || + (cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK))) { gic_set_pending_private(&s->gic, 0, value & 0x1ff); } break; |