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authorBernhard Beschow <shentey@gmail.com>2022-02-17 11:19:19 +0100
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2022-03-08 19:17:04 +0100
commita7fc9880514fcbc96c9825f040296fa59d7b3ccc (patch)
tree8e89e1720a9b8a04398edc7563da811ea5dc5fa2 /hw/mips/malta.c
parentc291635867a03c9217bd9610fe2a16d997932ec0 (diff)
downloadfocaccia-qemu-a7fc9880514fcbc96c9825f040296fa59d7b3ccc.tar.gz
focaccia-qemu-a7fc9880514fcbc96c9825f040296fa59d7b3ccc.zip
malta: Move PCI interrupt handling from gt64xxx_pci to piix4
Handling PCI interrupts in piix4 increases cohesion and reduces differences
between piix4 and piix3.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220217101924.15347-3-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'hw/mips/malta.c')
-rw-r--r--hw/mips/malta.c6
1 files changed, 1 insertions, 5 deletions
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index b770b8d367..13254dbc89 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -97,7 +97,6 @@ struct MaltaState {
 
     Clock *cpuclk;
     MIPSCPSState cps;
-    qemu_irq i8259[ISA_NUM_IRQS];
 };
 
 static struct _loaderparams {
@@ -1391,7 +1390,7 @@ void mips_malta_init(MachineState *machine)
     stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
 
     /* Northbridge */
-    pci_bus = gt64120_register(s->i8259);
+    pci_bus = gt64120_register();
     /*
      * The whole address space decoded by the GT-64120A doesn't generate
      * exception when accessing invalid memory. Create an empty slot to
@@ -1404,9 +1403,6 @@ void mips_malta_init(MachineState *machine)
 
     /* Interrupt controller */
     qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
-    for (int i = 0; i < ISA_NUM_IRQS; i++) {
-        s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
-    }
 
     /* generate SPD EEPROM data */
     generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);