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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-04-01 01:04:43 +0200 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-04-01 11:29:25 +0200 |
| commit | f0095c8ad93de7652aba36c4c713d9035417bea8 (patch) | |
| tree | 80aaf23ed9ab47381b8e49fa842ea969b5ab5e9a /hw/misc/aspeed_scu.c | |
| parent | 0f15892acaf3f50ecc20c6dad4b3ebdd701aa93e (diff) | |
| download | focaccia-qemu-f0095c8ad93de7652aba36c4c713d9035417bea8.tar.gz focaccia-qemu-f0095c8ad93de7652aba36c4c713d9035417bea8.zip | |
hw/misc/aspeed_scu: Set MemoryRegionOps::impl::access_size to 32-bit
All MemoryRegionOps::read/write() handlers switch over a 32-bit aligned value, because converted using TO_REG(), which is defined as: #define TO_REG(offset) ((offset) >> 2) So all implementations are 32-bit. Set min/max access_size accordingly. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Link: https://lore.kernel.org/qemu-devel/20250331230444.88295-2-philmd@linaro.org Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'hw/misc/aspeed_scu.c')
| -rw-r--r-- | hw/misc/aspeed_scu.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 76cfd91671..6703f3f969 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -427,6 +427,10 @@ static const MemoryRegionOps aspeed_ast2400_scu_ops = { .read = aspeed_scu_read, .write = aspeed_ast2400_scu_write, .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, .valid = { .min_access_size = 1, .max_access_size = 4, @@ -437,6 +441,8 @@ static const MemoryRegionOps aspeed_ast2500_scu_ops = { .read = aspeed_scu_read, .write = aspeed_ast2500_scu_write, .endianness = DEVICE_LITTLE_ENDIAN, + .impl.min_access_size = 4, + .impl.max_access_size = 4, .valid.min_access_size = 4, .valid.max_access_size = 4, .valid.unaligned = false, @@ -779,6 +785,8 @@ static const MemoryRegionOps aspeed_ast2600_scu_ops = { .read = aspeed_ast2600_scu_read, .write = aspeed_ast2600_scu_write, .endianness = DEVICE_LITTLE_ENDIAN, + .impl.min_access_size = 4, + .impl.max_access_size = 4, .valid.min_access_size = 4, .valid.max_access_size = 4, .valid.unaligned = false, @@ -906,6 +914,8 @@ static const MemoryRegionOps aspeed_ast2700_scu_ops = { .read = aspeed_ast2700_scu_read, .write = aspeed_ast2700_scu_write, .endianness = DEVICE_LITTLE_ENDIAN, + .impl.min_access_size = 4, + .impl.max_access_size = 4, .valid.min_access_size = 1, .valid.max_access_size = 8, .valid.unaligned = false, @@ -1028,6 +1038,8 @@ static const MemoryRegionOps aspeed_ast2700_scuio_ops = { .read = aspeed_ast2700_scuio_read, .write = aspeed_ast2700_scuio_write, .endianness = DEVICE_LITTLE_ENDIAN, + .impl.min_access_size = 4, + .impl.max_access_size = 4, .valid.min_access_size = 1, .valid.max_access_size = 8, .valid.unaligned = false, |