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| author | Peter Maydell <peter.maydell@linaro.org> | 2018-02-15 18:37:46 +0000 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-02-15 18:37:46 +0000 |
| commit | cc5a0ae03e0d011521ca5b32d3995a299b6b3ad3 (patch) | |
| tree | 66650bd76033948075563b3b09c07aed3a02fb84 /hw/misc/macio/cuda.c | |
| parent | f003d07337a6d4d02c43429b26a4270459afb51a (diff) | |
| parent | bade58166f4466546600d824a2695a00269d10eb (diff) | |
| download | focaccia-qemu-cc5a0ae03e0d011521ca5b32d3995a299b6b3ad3.tar.gz focaccia-qemu-cc5a0ae03e0d011521ca5b32d3995a299b6b3ad3.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180215-1' into staging
target-arm queue: * aspeed: code cleanup to use unimplemented_device * preparatory work for 'raspi3' RaspberryPi 3 machine model * more SVE prep work * v8M: add minor missing registers * v7M: fix bug where we weren't migrating v7m.other_sp * v7M: fix bugs in handling of interrupt registers for external interrupts beyond 32 # gpg: Signature made Thu 15 Feb 2018 18:34:40 GMT # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180215-1: raspi: Raspberry Pi 3 support bcm2836: Make CPU type configurable target/arm: Implement v8M MSPLIM and PSPLIM registers target/arm: Migrate v7m.other_sp target/arm: Add AIRCR to vmstate struct hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions target/arm: Implement writing to CONTROL_NS for v8M hw/intc/armv7m_nvic: Implement SCR hw/intc/armv7m_nvic: Implement cache ID registers hw/intc/armv7m_nvic: Implement v8M CPPWR register hw/intc/armv7m_nvic: Implement M profile cache maintenance ops hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC target/arm: Handle SVE registers when using clear_vec_high target/arm: Enforce access to ZCR_EL at translation target/arm: Suppress TB end for FPCR/FPSR target/arm: Enforce FP access to FPCR/FPSR target/arm: Remove ARM_CP_64BIT from ZCR_EL registers hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.io hw/arm/aspeed: directly map the serial device to the system address space Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/misc/macio/cuda.c')
0 files changed, 0 insertions, 0 deletions