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authorLeon Alrae <leon.alrae@imgtec.com>2016-06-09 10:46:51 +0100
committerLeon Alrae <leon.alrae@imgtec.com>2016-07-12 09:10:15 +0100
commitdff94251f02708d2ef9aee5149abd69f039e4a13 (patch)
treeb1bbcc4b3be27605993db87de547bd972d74d86a /hw/misc/mips_cpc.c
parent89777fd10fc3dd573c3b4d1b2efdd10af823c001 (diff)
downloadfocaccia-qemu-dff94251f02708d2ef9aee5149abd69f039e4a13.tar.gz
focaccia-qemu-dff94251f02708d2ef9aee5149abd69f039e4a13.zip
hw/mips_cpc: make VP correctly start from the reset vector
When VP enters the Run state it starts execution from the reset vector.
Currently used CPU_INTERRUPT_WAKE does not do that if reset exception
base has been modified. Therefore fix that by simply resetting given VP.

Drop the usage of CPU_INTERRUPT_WAKE also in VP_STOP and instead raise
the CPU_INTERRUPT_HALT to halt a VP.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'hw/misc/mips_cpc.c')
-rw-r--r--hw/misc/mips_cpc.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c
index e6a35dd6a0..6d345745f6 100644
--- a/hw/misc/mips_cpc.c
+++ b/hw/misc/mips_cpc.c
@@ -37,7 +37,7 @@ static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)
     CPU_FOREACH(cs) {
         uint64_t i = 1ULL << cs->cpu_index;
         if (i & vp_run & ~cpc->vp_running) {
-            cpu_interrupt(cs, CPU_INTERRUPT_WAKE);
+            cpu_reset(cs);
             cpc->vp_running |= i;
         }
     }
@@ -50,8 +50,7 @@ static void cpc_stop_vp(MIPSCPCState *cpc, uint64_t vp_stop)
     CPU_FOREACH(cs) {
         uint64_t i = 1ULL << cs->cpu_index;
         if (i & vp_stop & cpc->vp_running) {
-            cs->halted = 1;
-            cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
+            cpu_interrupt(cs, CPU_INTERRUPT_HALT);
             cpc->vp_running &= ~i;
         }
     }