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| author | Peter Maydell <peter.maydell@linaro.org> | 2024-02-06 13:29:20 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-02-15 14:32:38 +0000 |
| commit | fe31d6c72d0046eb633db51dc1d8fb9b231d270f (patch) | |
| tree | 268c3f957692b4a0528bda5032bd523f98e1a880 /hw/misc/mps2-scc.c | |
| parent | b2f24983db11dd1345db95f54a6d1dce184224a3 (diff) | |
| download | focaccia-qemu-fe31d6c72d0046eb633db51dc1d8fb9b231d270f.tar.gz focaccia-qemu-fe31d6c72d0046eb633db51dc1d8fb9b231d270f.zip | |
target/arm: The Cortex-R52 has a read-only CBAR
The Cortex-R52 implements the Configuration Base Address Register (CBAR), as a read-only register. Add ARM_FEATURE_CBAR_RO to this CPU type, so that our implementation provides the register and the associated qdev property. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240206132931.38376-3-peter.maydell@linaro.org
Diffstat (limited to 'hw/misc/mps2-scc.c')
0 files changed, 0 insertions, 0 deletions