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| author | Chen Baozi <chenbaozi@phytium.com.cn> | 2023-03-13 11:39:36 +0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-03-21 11:54:39 +0000 |
| commit | 0b903369951cac12ccdfc66a7520b413eca1bb62 (patch) | |
| tree | 10b2d2dd1e0d58fad88ccdfc6347fb333d24fb4e /hw/misc/omap_gpmc.c | |
| parent | aa9e7fa4689d1becb2faf67f65aafcbcf664f1ce (diff) | |
| download | focaccia-qemu-0b903369951cac12ccdfc66a7520b413eca1bb62.tar.gz focaccia-qemu-0b903369951cac12ccdfc66a7520b413eca1bb62.zip | |
target/arm: Add Neoverse-N1 registers
Add implementation defined registers for neoverse-n1 which would be accessed by TF-A. Since there is no DSU in Qemu, CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition. Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Message-id: 20230313033936.585669-1-chenbaozi@phytium.com.cn Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/misc/omap_gpmc.c')
0 files changed, 0 insertions, 0 deletions