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| author | Bin Meng <bin.meng@windriver.com> | 2020-09-03 18:40:12 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-09-09 15:54:19 -0700 |
| commit | 89ece6f76f089bc415fc4b8c78f7dbe74113380c (patch) | |
| tree | bbebaf8350b1b2ca6d9331782dd7d6b544b853c9 /hw/misc/sifive_e_prci.c | |
| parent | 834e027a3452e1c139c5400cae550c6c5a340b28 (diff) | |
| download | focaccia-qemu-89ece6f76f089bc415fc4b8c78f7dbe74113380c.tar.gz focaccia-qemu-89ece6f76f089bc415fc4b8c78f7dbe74113380c.zip | |
hw/riscv: Move sifive_e_prci model to hw/misc
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_e_prci model to hw/misc directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-2-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to '')
| -rw-r--r-- | hw/misc/sifive_e_prci.c (renamed from hw/riscv/sifive_e_prci.c) | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/sifive_e_prci.c b/hw/misc/sifive_e_prci.c index 17dfa74715..8ec4ee4b41 100644 --- a/hw/riscv/sifive_e_prci.c +++ b/hw/misc/sifive_e_prci.c @@ -24,7 +24,7 @@ #include "qemu/log.h" #include "qemu/module.h" #include "hw/hw.h" -#include "hw/riscv/sifive_e_prci.h" +#include "hw/misc/sifive_e_prci.h" static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int size) { |