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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-04-20 17:32:29 +0100 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-04-20 17:39:17 +0100 |
| commit | 65ed2ed90d9d81fd4b639029be850ea5651f919f (patch) | |
| tree | ed9906ffac0ec1e410f0a22338c3a5380eb697b5 /hw/net/cadence_gem.c | |
| parent | 2c4a7cc5afb1bfc1728a39abd951ddd7714c476e (diff) | |
| download | focaccia-qemu-65ed2ed90d9d81fd4b639029be850ea5651f919f.tar.gz focaccia-qemu-65ed2ed90d9d81fd4b639029be850ea5651f919f.zip | |
target/arm: Add assertion about FSC format for syndrome registers
In tlb_fill() we construct a syndrome register value from a fault status register value which is filled in by arm_tlb_fill(). arm_tlb_fill() returns FSR values which might be in the format used with short-format page descriptors, or the format used with long-format (LPAE) descriptors. The syndrome register always uses LPAE-format FSR status codes. It isn't actually possible to end up delivering a syndrome register value to the guest for a fault which is reported with a short-format FSR (that kind of stage 1 fault will only happen for an AArch32 translation regime which doesn't have a syndrome register, and can never be redirected to an AArch64 or Hyp exception level). Add an assertion which checks this, and adjust the code so that we construct a syndrome with an invalid status code, rather than allowing set bits in the FSR input to randomly corrupt other fields in the syndrome. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1491486152-24304-1-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'hw/net/cadence_gem.c')
0 files changed, 0 insertions, 0 deletions