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authorPhilippe Mathieu-Daudé <philmd@linaro.org>2023-10-12 10:35:09 +0200
committerPhilippe Mathieu-Daudé <philmd@linaro.org>2024-09-13 20:10:49 +0200
commit13a07eb146c860f85f6fe665dd492f4f89146ba8 (patch)
tree8530cb37c637d8ba5c6270244f11bca53e6d2f43 /hw/pci-host/designware.c
parent28ae3179fc52d2e4d870b635c4a412aab99759e7 (diff)
downloadfocaccia-qemu-13a07eb146c860f85f6fe665dd492f4f89146ba8.tar.gz
focaccia-qemu-13a07eb146c860f85f6fe665dd492f4f89146ba8.zip
hw/pci-host/designware: Declare CPU QOM types using DEFINE_TYPES() macro
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.

Remove a pointless structure declaration in "designware.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-Id: <20231012121857.31873-2-philmd@linaro.org>
Diffstat (limited to 'hw/pci-host/designware.c')
-rw-r--r--hw/pci-host/designware.c39
1 files changed, 17 insertions, 22 deletions
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index a8210e9bbb..2bd467b34d 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -752,28 +752,23 @@ static void designware_pcie_host_init(Object *obj)
     qdev_prop_set_bit(DEVICE(root), "multifunction", false);
 }
 
-static const TypeInfo designware_pcie_root_info = {
-    .name = TYPE_DESIGNWARE_PCIE_ROOT,
-    .parent = TYPE_PCI_BRIDGE,
-    .instance_size = sizeof(DesignwarePCIERoot),
-    .class_init = designware_pcie_root_class_init,
-    .interfaces = (InterfaceInfo[]) {
-        { INTERFACE_PCIE_DEVICE },
-        { }
+static const TypeInfo designware_pcie_types[] = {
+    {
+        .name           = TYPE_DESIGNWARE_PCIE_HOST,
+        .parent         = TYPE_PCI_HOST_BRIDGE,
+        .instance_size  = sizeof(DesignwarePCIEHost),
+        .instance_init  = designware_pcie_host_init,
+        .class_init     = designware_pcie_host_class_init,
+    }, {
+        .name           = TYPE_DESIGNWARE_PCIE_ROOT,
+        .parent         = TYPE_PCI_BRIDGE,
+        .instance_size  = sizeof(DesignwarePCIERoot),
+        .class_init     = designware_pcie_root_class_init,
+        .interfaces     = (InterfaceInfo[]) {
+            { INTERFACE_PCIE_DEVICE },
+            { }
+        },
     },
 };
 
-static const TypeInfo designware_pcie_host_info = {
-    .name       = TYPE_DESIGNWARE_PCIE_HOST,
-    .parent     = TYPE_PCI_HOST_BRIDGE,
-    .instance_size = sizeof(DesignwarePCIEHost),
-    .instance_init = designware_pcie_host_init,
-    .class_init = designware_pcie_host_class_init,
-};
-
-static void designware_pcie_register(void)
-{
-    type_register_static(&designware_pcie_root_info);
-    type_register_static(&designware_pcie_host_info);
-}
-type_init(designware_pcie_register)
+DEFINE_TYPES(designware_pcie_types)