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authorNicholas Piggin <npiggin@gmail.com>2023-12-27 23:53:25 +1000
committerNicholas Piggin <npiggin@gmail.com>2024-03-13 02:47:04 +1000
commit8b0e3fb835511fe65cfb0df79fc17df2fede4805 (patch)
tree710431fdced4eff4f3f9b39f7c7ffa4dca7298fe /hw/ppc
parent17aa684ff7941f44af57cbb1c7b46bf5dc4f4fe2 (diff)
downloadfocaccia-qemu-8b0e3fb835511fe65cfb0df79fc17df2fede4805.tar.gz
focaccia-qemu-8b0e3fb835511fe65cfb0df79fc17df2fede4805.zip
ppc/spapr: Adjust ibm,pa-features for POWER9
"MMR" and "SPR SO" are not implemented in POWER9, so clear those bits.
HTM is not set by default, and only later if the cap is set, so remove
the comment that suggests otherwise.

Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'hw/ppc')
-rw-r--r--hw/ppc/spapr.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 4192cd8d6c..5bbd0d7a04 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -258,14 +258,14 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
         0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
         /* 16: Vector */
         0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
-        /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
+        /* 18: Vec. Scalar, 20: Vec. XOR */
         0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
         /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
         0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
-        /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
-        0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
-        /* 36: SPR SO, 40: Radix MMU */
-        0x80, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
+        /* 32: LE atomic, 34: EBB + ext EBB */
+        0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
+        /* 40: Radix MMU */
+        0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
         /* 42: PM, 44: PC RA, 46: SC vec'd */
         0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
         /* 48: SIMD, 50: QP BFP, 52: String */