diff options
| author | Paul Brook <paul@codesourcery.com> | 2009-11-13 03:30:33 +0000 |
|---|---|---|
| committer | Paul Brook <paul@codesourcery.com> | 2009-11-13 04:04:18 +0000 |
| commit | 26e92f65525ef4446a500d85e185cf78835922aa (patch) | |
| tree | 4297dd3341245566647126edbd5fee80a5ef24af /hw/realview.c | |
| parent | dbe73d7f3b85b9c1473d1400bc29ff495d8c1322 (diff) | |
| download | focaccia-qemu-26e92f65525ef4446a500d85e185cf78835922aa.tar.gz focaccia-qemu-26e92f65525ef4446a500d85e185cf78835922aa.zip | |
Realview/EB procid hacks
Guess core tile ID based on CPU type. Signed-off-by: Paul Brook <paul@codesourcery.com>
Diffstat (limited to 'hw/realview.c')
| -rw-r--r-- | hw/realview.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/hw/realview.c b/hw/realview.c index 95ad727d43..a14c8a08c9 100644 --- a/hw/realview.c +++ b/hw/realview.c @@ -51,6 +51,7 @@ static void realview_init(ram_addr_t ram_size, int done_smc = 0; qemu_irq cpu_irq[4]; int ncpu; + uint32_t proc_id = 0; if (!cpu_model) cpu_model = "arm926"; @@ -73,13 +74,22 @@ static void realview_init(ram_addr_t ram_size, qemu_register_reset(secondary_cpu_reset, env); } } + if (arm_feature(env, ARM_FEATURE_V7)) { + proc_id = 0x0e000000; + } else if (arm_feature(env, ARM_FEATURE_V6K)) { + proc_id = 0x06000000; + } else if (arm_feature(env, ARM_FEATURE_V6)) { + proc_id = 0x04000000; + } else { + proc_id = 0x02000000; + } ram_offset = qemu_ram_alloc(ram_size); /* ??? RAM should repeat to fill physical memory space. */ /* SDRAM at address zero. */ cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); - arm_sysctl_init(0x10000000, 0xc1400400); + arm_sysctl_init(0x10000000, 0xc1400400, proc_id); if (ncpu == 1) { /* ??? The documentation says GIC1 is nFIQ and either GIC2 or GIC3 |