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authorTomasz Jeznach <tjeznach@rivosinc.com>2024-10-16 17:40:33 -0300
committerAlistair Francis <alistair.francis@wdc.com>2024-10-31 13:51:24 +1000
commit69a9ae483696e185889edaeddacf46afd9110bc6 (patch)
treec30f49b0d76606c15f86e0b80f4fad9db6d963b6 /hw/riscv/riscv-iommu.h
parent9d085a1c3cb2b6a1ee77d5f6e0ca20241208acd8 (diff)
downloadfocaccia-qemu-69a9ae483696e185889edaeddacf46afd9110bc6.tar.gz
focaccia-qemu-69a9ae483696e185889edaeddacf46afd9110bc6.zip
hw/riscv/riscv-iommu: add ATS support
Add PCIe Address Translation Services (ATS) capabilities to the IOMMU.
This will add support for ATS translation requests in Fault/Event
queues, Page-request queue and IOATC invalidations.

Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241016204038.649340-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/riscv-iommu.h')
-rw-r--r--hw/riscv/riscv-iommu.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h
index 9f15f3b27f..da3f03440c 100644
--- a/hw/riscv/riscv-iommu.h
+++ b/hw/riscv/riscv-iommu.h
@@ -37,6 +37,7 @@ struct RISCVIOMMUState {
 
     bool enable_off;      /* Enable out-of-reset OFF mode (DMA disabled) */
     bool enable_msi;      /* Enable MSI remapping */
+    bool enable_ats;      /* Enable ATS support */
     bool enable_s_stage;  /* Enable S/VS-Stage translation */
     bool enable_g_stage;  /* Enable G-Stage translation */