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| author | Bin Meng <bin.meng@windriver.com> | 2020-06-15 17:50:40 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-06-19 08:25:27 -0700 |
| commit | 49093916d37f663e86316ec54cb77d5515bb973f (patch) | |
| tree | b8bb02546172fbf903ebe552396ce649742e871f /hw/riscv/sifive_u.c | |
| parent | 17aad9f276953c1eaf0750faf4758fd2f5ebeb84 (diff) | |
| download | focaccia-qemu-49093916d37f663e86316ec54cb77d5515bb973f.tar.gz focaccia-qemu-49093916d37f663e86316ec54cb77d5515bb973f.zip | |
hw/riscv: sifive_u: Sort the SoC memmap table entries
Move the flash and DRAM to the end of the SoC memmap table. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1592268641-7478-5-git-send-email-bmeng.cn@gmail.com Message-Id: <1592268641-7478-5-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/sifive_u.c')
| -rw-r--r-- | hw/riscv/sifive_u.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index eb767aa863..b9d0a6901a 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -80,10 +80,10 @@ static const struct MemmapEntry { [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, [SIFIVE_U_GPIO] = { 0x10060000, 0x1000 }, [SIFIVE_U_OTP] = { 0x10070000, 0x1000 }, - [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 }, - [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, [SIFIVE_U_GEM] = { 0x10090000, 0x2000 }, [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 }, + [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 }, + [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, }; #define OTP_SERIAL 1 |