Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging

* target/riscv: clean up supported MMU modes, declarative CPU definitions,
  remove .instance_post_init (reviewed by Alistair)
* qom: reverse order of instance_post_init calls
* qapi/misc-target: doc and standard improvements for SGX
* hw/pci-host/gt64120: Fix endianness handling
* i386/hvf: Make CPUID_HT supported
* i386/tcg: Make CPUID_HT and CPUID_EXT3_CMP_LEG supported

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# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
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* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (35 commits)
  qom: reverse order of instance_post_init calls
  target/riscv: remove .instance_post_init
  target/riscv: convert Xiangshan Nanhu to RISCVCPUDef
  target/riscv: convert Ventana V1 to RISCVCPUDef
  target/riscv: convert TT Ascalon to RISCVCPUDef
  target/riscv: convert THead C906 to RISCVCPUDef
  target/riscv: generalize custom CSR functionality
  target/riscv: th: make CSR insertion test a bit more intuitive
  target/riscv: convert SiFive U models to RISCVCPUDef
  target/riscv: convert ibex CPU models to RISCVCPUDef
  target/riscv: convert SiFive E CPU models to RISCVCPUDef
  target/riscv: convert dynamic CPU models to RISCVCPUDef
  target/riscv: convert bare CPU models to RISCVCPUDef
  target/riscv: convert profile CPU models to RISCVCPUDef
  target/riscv: convert abstract CPU classes to RISCVCPUDef
  target/riscv: add more RISCVCPUDef fields
  target/riscv: include default value in cpu_cfg_fields.h.inc
  target/riscv: move RISCVCPUConfig fields to a header file
  target/riscv: merge riscv_cpu_class_init with the class_base function
  target/riscv: store RISCVCPUDef struct directly in the class
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

1 files changed, 2 insertions, 3 deletions

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 0dcced1b49..cf280a92e5 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -237,10 +237,10 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
     uint32_t cpu_phandle;
     MachineState *ms = MACHINE(s);
     bool is_32_bit = riscv_is_32bit(&s->soc[0]);
-    uint8_t satp_mode_max;
 
     for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
         RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu];
+        int8_t satp_mode_max = cpu_ptr->cfg.max_satp_mode;
         g_autofree char *cpu_name = NULL;
         g_autofree char *core_name = NULL;
         g_autofree char *intc_name = NULL;
@@ -252,8 +252,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
             s->soc[socket].hartid_base + cpu);
         qemu_fdt_add_subnode(ms->fdt, cpu_name);
 
-        if (cpu_ptr->cfg.satp_mode.supported != 0) {
-            satp_mode_max = satp_mode_max_from_map(cpu_ptr->cfg.satp_mode.map);
+        if (satp_mode_max != -1) {
             sv_name = g_strdup_printf("riscv,%s",
                                       satp_mode_str(satp_mode_max, is_32_bit));
             qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name);