diff options
| author | Joel Stanley <joel@jms.id.au> | 2025-06-04 12:24:45 +0930 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-07-04 21:09:49 +1000 |
| commit | 4f1572d6f191f4618b30be3fda7344461910a03f (patch) | |
| tree | 875bd33a6acb023a41640a0a13c7d8bd1e7b9cbf /hw/riscv | |
| parent | 08454fc3f5e43338c2e13dc040a2ebe77834945f (diff) | |
| download | focaccia-qemu-4f1572d6f191f4618b30be3fda7344461910a03f.tar.gz focaccia-qemu-4f1572d6f191f4618b30be3fda7344461910a03f.zip | |
hw/riscv/virt: Use setprop_sized_cells for uart
The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20250604025450.85327-10-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv')
| -rw-r--r-- | hw/riscv/virt.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index b59f10dabe..7c38a90480 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -966,9 +966,9 @@ static void create_fdt_uart(RISCVVirtState *s, s->memmap[VIRT_UART0].base); qemu_fdt_add_subnode(ms->fdt, name); qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); - qemu_fdt_setprop_cells(ms->fdt, name, "reg", - 0x0, s->memmap[VIRT_UART0].base, - 0x0, s->memmap[VIRT_UART0].size); + qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", + 2, s->memmap[VIRT_UART0].base, + 2, s->memmap[VIRT_UART0].size); qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); if (s->aia_type == VIRT_AIA_TYPE_NONE) { |