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authorJoel Stanley <joel@jms.id.au>2025-06-04 12:24:42 +0930
committerAlistair Francis <alistair.francis@wdc.com>2025-07-04 21:09:49 +1000
commit507161b5f53ae37e2aeeb99e558485146546331e (patch)
tree6f602599fb152f879f54b71ef830ebd317642d04 /hw/riscv
parentdd3d4fd9923082d8d2ad6ed71b4be05dad36b601 (diff)
downloadfocaccia-qemu-507161b5f53ae37e2aeeb99e558485146546331e.tar.gz
focaccia-qemu-507161b5f53ae37e2aeeb99e558485146546331e.zip
hw/riscv/virt: Use setprop_sized_cells for plic
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.

Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-ID: <20250604025450.85327-7-joel@jms.id.au>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv')
-rw-r--r--hw/riscv/virt.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4fd966a342..67e60eec1f 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -493,8 +493,8 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
                          s->soc[socket].num_harts * sizeof(uint32_t) * 4);
     }
 
-    qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg",
-        0x0, plic_addr, 0x0, s->memmap[VIRT_PLIC].size);
+    qemu_fdt_setprop_sized_cells(ms->fdt, plic_name, "reg",
+                                 2, plic_addr, 2, s->memmap[VIRT_PLIC].size);
     qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev",
                           VIRT_IRQCHIP_NUM_SOURCES - 1);
     riscv_socket_fdt_write_id(ms, plic_name, socket);