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| author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-27 19:42:35 +0000 |
|---|---|---|
| committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-27 19:42:35 +0000 |
| commit | dd4131b39492bd91dc87d216e761ca4cf210fb67 (patch) | |
| tree | a3853bd3cff8adb62c3e369ad8d20a0d6460d441 /hw/slavio_intctl.c | |
| parent | c4a7060cf70e2e72f44a98307f453eba07e09bea (diff) | |
| download | focaccia-qemu-dd4131b39492bd91dc87d216e761ca4cf210fb67.tar.gz focaccia-qemu-dd4131b39492bd91dc87d216e761ca4cf210fb67.zip | |
Interrupt debugging DPRINTFs
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2881 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/slavio_intctl.c')
| -rw-r--r-- | hw/slavio_intctl.c | 32 |
1 files changed, 22 insertions, 10 deletions
diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c index d89f863156..acde370e5c 100644 --- a/hw/slavio_intctl.c +++ b/hw/slavio_intctl.c @@ -71,18 +71,22 @@ static void slavio_check_interrupts(void *opaque); static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr) { SLAVIO_INTCTLState *s = opaque; - uint32_t saddr; + uint32_t saddr, ret; int cpu; cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12; saddr = (addr & INTCTL_MAXADDR) >> 2; switch (saddr) { case 0: - return s->intreg_pending[cpu]; + ret = s->intreg_pending[cpu]; + break; default: - break; + ret = 0; + break; } - return 0; + DPRINTF("read cpu %d reg 0x%x = %x\n", addr, ret); + + return ret; } static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) @@ -93,6 +97,7 @@ static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12; saddr = (addr & INTCTL_MAXADDR) >> 2; + DPRINTF("write cpu %d reg 0x%x = %x\n", cpu, addr, val); switch (saddr) { case 1: // clear pending softints if (val & 0x4000) @@ -128,20 +133,26 @@ static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = { static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr) { SLAVIO_INTCTLState *s = opaque; - uint32_t saddr; + uint32_t saddr, ret; saddr = (addr & INTCTLM_MAXADDR) >> 2; switch (saddr) { case 0: - return s->intregm_pending & 0x7fffffff; + ret = s->intregm_pending & 0x7fffffff; + break; case 1: - return s->intregm_disabled; + ret = s->intregm_disabled; + break; case 4: - return s->target_cpu; + ret = s->target_cpu; + break; default: - break; + ret = 0; + break; } - return 0; + DPRINTF("read system reg 0x%x = %x\n", addr, ret); + + return ret; } static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) @@ -150,6 +161,7 @@ static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uin uint32_t saddr; saddr = (addr & INTCTLM_MASK) >> 2; + DPRINTF("write system reg 0x%x = %x\n", addr, val); switch (saddr) { case 2: // clear (enable) // Force clear unused bits |