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| author | Cédric Le Goater <clg@kaod.org> | 2018-06-15 14:57:15 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-06-15 15:23:34 +0100 |
| commit | 2151b044fdca74a4fe7148f302ba9d6191516744 (patch) | |
| tree | 8164c128ed43d434f7b56264f6cb9852ee6f9fe6 /hw/sparc/sun4m_iommu.c | |
| parent | acd9575e59da1bfc21a1feccb00c5dddd45328f7 (diff) | |
| download | focaccia-qemu-2151b044fdca74a4fe7148f302ba9d6191516744.tar.gz focaccia-qemu-2151b044fdca74a4fe7148f302ba9d6191516744.zip | |
m25p80: add support for two bytes WRSR for Macronix chips
On Macronix chips, two bytes can written to the WRSR. First byte will configure the status register and the second the configuration register. It is important to save the configuration value as it contains the dummy cycle setting when using dual or quad IO mode. Signed-off-by: Cédric Le Goater <clg@kaod.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/sparc/sun4m_iommu.c')
0 files changed, 0 insertions, 0 deletions