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authorPeter Maydell <peter.maydell@linaro.org>2019-08-16 13:58:02 +0100
committerPeter Maydell <peter.maydell@linaro.org>2019-09-03 16:20:34 +0100
commit0710b2fa84a4aeb925422e1e88edac49ed407c79 (patch)
tree3ddb2aed17a200222a3a61ec8ff4abdf5b596849 /hw/timer/aspeed_timer.c
parent37ff584c15bc3e1dd2c26b1998f00ff87189538c (diff)
downloadfocaccia-qemu-0710b2fa84a4aeb925422e1e88edac49ed407c79.tar.gz
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target/arm: Take exceptions on ATS instructions when needed
The translation table walk for an ATS instruction can result in
various faults.  In general these are just reported back via the
PAR_EL1 fault status fields, but in some cases the architecture
requires that the fault is turned into an exception:
 * synchronous stage 2 faults of any kind during AT S1E0* and
   AT S1E1* instructions executed from NS EL1 fault to EL2 or EL3
 * synchronous external aborts are taken as Data Abort exceptions

(This is documented in the v8A Arm ARM DDI0487A.e D5.2.11 and
G5.13.4.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20190816125802.25877-3-peter.maydell@linaro.org
Diffstat (limited to 'hw/timer/aspeed_timer.c')
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