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authorPeter Maydell <peter.maydell@linaro.org>2018-09-25 14:02:32 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-09-25 15:13:24 +0100
commitb187e20f9b902b611ca9288cef5c490cbb2d91dd (patch)
treecbf14228e091b5100f2e9183c44cc417332e325e /hw/timer/aspeed_timer.c
parent5d026de8b6aeb4d494c21ac32112c2821bd05422 (diff)
downloadfocaccia-qemu-b187e20f9b902b611ca9288cef5c490cbb2d91dd.tar.gz
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hw/net/pcnet-pci: Unify pcnet_ioport_read/write and pcnet_mmio_read/write
The only difference between our implementation of the pcnet ioport
accessors and the mmio accessors is that the former check BCR_DWIO to
see what access widths are permitted for addresses in the aprom range
(0x0..0xf). In fact our failure to do this in the mmio accessors
is a bug (one which was fixed for the ioport accessors in
commit 7ba79741970 in 2011).

The data sheet for the Am79C970A does not describe the DWIO
bit as only applying for I/O space mapped I/O resources and
not memory mapped I/O resources, and our MMIO accessors already
honour DWIO for accesses in the 0x10..0x1f range (since the
pcnet_ioport_{read,write}{w,l} functions check it).

The data sheet for the later but compatible Am79C976 is clearer:
it states specifically "DWIO mode applies to both I/O- and
memory-mapped acceses." This seems to be reasonable evidence
in favour of interpretating the Am79C970A spec as being the same.

(NB: Linux's pcnet driver only supports I/O accesses, so the
MMIO access part of this device is probably untested anyway.)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/timer/aspeed_timer.c')
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