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| author | Jamin Lin <jamin_lin@aspeedtech.com> | 2024-11-14 17:48:39 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-01-27 09:38:15 +0100 |
| commit | bf8a471a38774800d77f58949bcaea4ca26390a7 (patch) | |
| tree | af7c328cc4000bb8e5f05c08d7478d5f3fc81c32 /hw/timer/aspeed_timer.c | |
| parent | 134d9e5c0c4ae2fe64817a185730ec8b7835d573 (diff) | |
| download | focaccia-qemu-bf8a471a38774800d77f58949bcaea4ca26390a7.tar.gz focaccia-qemu-bf8a471a38774800d77f58949bcaea4ca26390a7.zip | |
hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB
The Write Protect pin of SDHCI model is default active low to match the SDHCI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). According to the design of AST2600 EVB, the Write Protected pin is active high by default. To support it, introduces a new "sdhci_wp_inverted" property in ASPEED MACHINE State and set it true for AST2600 EVB and set "wp_inverted" property true of sdhci-generic model. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20241114094839.4128404-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'hw/timer/aspeed_timer.c')
0 files changed, 0 insertions, 0 deletions