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| author | Prasad J Pandit <pjp@fedoraproject.org> | 2017-02-28 12:08:14 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-02-28 12:08:14 +0000 |
| commit | 6e86d90352adf6cb08295255220295cf23c4286e (patch) | |
| tree | c1cb502bf997466041be926b4d320636b73be167 /hw/timer/imx_gpt.c | |
| parent | 8b20aefac4ee8874bb9c8826e4b30e1dc8cd7511 (diff) | |
| download | focaccia-qemu-6e86d90352adf6cb08295255220295cf23c4286e.tar.gz focaccia-qemu-6e86d90352adf6cb08295255220295cf23c4286e.zip | |
sd: sdhci: check transfer mode register in multi block transfer
In the SDHCI protocol, the transfer mode register value is used during multi block transfer to check if block count register is enabled and should be updated. Transfer mode register could be set such that, block count register would not be updated, thus leading to an infinite loop. Add check to avoid it. Reported-by: Wjjzhang <wjjzhang@tencent.com> Reported-by: Jiang Xin <jiangxin1@huawei.com> Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org> Message-id: 20170214185225.7994-3-ppandit@redhat.com Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/timer/imx_gpt.c')
0 files changed, 0 insertions, 0 deletions