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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-05-04 09:28:21 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-05-11 11:05:52 +0100 |
| commit | 27d6dea3d702b4f9cefacfc8438a9478c03092e4 (patch) | |
| tree | a8b2a2aed46997ef9631814bebf364ff4d182896 /hw/timer/trace-events | |
| parent | 54595a5731ed7c94491008b0d3835ad3f786dbcc (diff) | |
| download | focaccia-qemu-27d6dea3d702b4f9cefacfc8438a9478c03092e4.tar.gz focaccia-qemu-27d6dea3d702b4f9cefacfc8438a9478c03092e4.zip | |
hw/timer/nrf51_timer: Display timer ID in trace events
The NRF51 series SoC have 3 timer peripherals, each having 4 counters. To help differentiate which peripheral is accessed, display the timer ID in the trace events. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200504072822.18799-4-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/timer/trace-events')
| -rw-r--r-- | hw/timer/trace-events | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/timer/trace-events b/hw/timer/trace-events index 29fda7870e..43b605cc75 100644 --- a/hw/timer/trace-events +++ b/hw/timer/trace-events @@ -67,8 +67,8 @@ cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset" # nrf51_timer.c -nrf51_timer_read(uint64_t addr, uint32_t value, unsigned size) "read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" -nrf51_timer_write(uint64_t addr, uint32_t value, unsigned size) "write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" +nrf51_timer_read(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" +nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" # bcm2835_systmr.c bcm2835_systmr_irq(bool enable) "timer irq state %u" |