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| author | Sairaj Kodilkar <sarunkod@amd.com> | 2025-02-07 10:23:54 +0530 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2025-02-21 07:18:42 -0500 |
| commit | 3684717b7407cc395dc9bf522e193dbc85293dee (patch) | |
| tree | 837d22d32f093e1040ca2a1f431dae224e93da85 /hw/virtio/vhost-shadow-virtqueue.c | |
| parent | 63dc0b8647391b372f3bb38ff1066f6b4a5e6ea1 (diff) | |
| download | focaccia-qemu-3684717b7407cc395dc9bf522e193dbc85293dee.tar.gz focaccia-qemu-3684717b7407cc395dc9bf522e193dbc85293dee.zip | |
amd_iommu: Use correct bitmask to set capability BAR
AMD IOMMU provides the base address of control registers through
IVRS table and PCI capability. Since this base address is of 64 bit,
use 32 bits mask (instead of 16 bits) to set BAR low and high.
Fixes: d29a09ca68 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Sairaj Kodilkar <sarunkod@amd.com>
Reviewed-by: Vasant Hegde <vasant.hegde@amd.com>
Message-Id: <20250207045354.27329-3-sarunkod@amd.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/virtio/vhost-shadow-virtqueue.c')
0 files changed, 0 insertions, 0 deletions