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authorRichard Henderson <richard.henderson@linaro.org>2025-05-03 13:17:17 -0700
committerRichard Henderson <richard.henderson@linaro.org>2025-05-28 08:08:47 +0100
commitbdf26b5d16dd2264553308aa6bbf24b4749fcc07 (patch)
tree9a6d08fac93be2f40af00d0a9bd27f6e5cc1bf66 /include/accel/tcg/cpu-ops.h
parenteb978e50e42f3439e7a7a104e76aafc81bc4a028 (diff)
downloadfocaccia-qemu-bdf26b5d16dd2264553308aa6bbf24b4749fcc07.tar.gz
focaccia-qemu-bdf26b5d16dd2264553308aa6bbf24b4749fcc07.zip
accel/tcg: Add TCGCPUOps.pointer_wrap
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include/accel/tcg/cpu-ops.h')
-rw-r--r--include/accel/tcg/cpu-ops.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h
index cd22e5d5b9..83b2c2c864 100644
--- a/include/accel/tcg/cpu-ops.h
+++ b/include/accel/tcg/cpu-ops.h
@@ -223,6 +223,13 @@ struct TCGCPUOps {
                      MMUAccessType access_type, int mmu_idx,
                      bool probe, uintptr_t retaddr);
     /**
+     * @pointer_wrap:
+     *
+     * We have incremented @base to @result, resulting in a page change.
+     * For the current cpu state, adjust @result for possible overflow.
+     */
+    vaddr (*pointer_wrap)(CPUState *cpu, int mmu_idx, vaddr result, vaddr base);
+    /**
      * @do_transaction_failed: Callback for handling failed memory transactions
      * (ie bus faults or external aborts; not MMU faults)
      */