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| author | Peter Maydell <peter.maydell@linaro.org> | 2024-01-30 15:53:37 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-01-30 15:53:37 +0000 |
| commit | 1c8e621f097362d0a28c65fa2f31054b47a5282b (patch) | |
| tree | d161f9b0f9007281ebf871e6dc034fc16c462e8d /include/exec/cpu-common.h | |
| parent | 11be70677c70fdccd452a3233653949b79e97908 (diff) | |
| parent | ec1d32af123e7f13d98754a72bcaa7aa8c8e9d27 (diff) | |
| download | focaccia-qemu-1c8e621f097362d0a28c65fa2f31054b47a5282b.tar.gz focaccia-qemu-1c8e621f097362d0a28c65fa2f31054b47a5282b.zip | |
Merge tag 'pull-tcg-20240130' of https://gitlab.com/rth7680/qemu into staging
linux-user: Allow gdbstub to ignore page protection cpu-exec: simplify jump cache management include/exec: Cleanups toward building accel/tcg once # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmW4LXcdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+CgAf8CdqkvKsUK9/5bu99 # 9E4kRBkR8KqWYvBfRs4IFmjoEdEa4sCujWrHliOcW7Kh+XlVyAPI9rZG32QkxCEQ # hi9WXieXjfPLTTmrbeiq7cwxztSj8Z55wwvbxkrtFyGDQ0AMccp49tAvfejEb6VD # Ssx96nWQDgryLrn+My+wMQjl9aVKUWp5vB8k12aAcpRXPH2yoGE2JHAZ1C743nA6 # rShiJAT78HwERcMXDeYmmriYg0s4Z4+A6ErTiXDnFgj87YanHZc0I/55G5Sh+pW8 # REicD3jwS0GHOOHL0K781FopE1wTM442GLVxobXoxUXsHEiO+3TK5JdEIqvSstYA # fRB8Pg== # =xZOe # -----END PGP SIGNATURE----- # gpg: Signature made Mon 29 Jan 2024 22:57:59 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20240130' of https://gitlab.com/rth7680/qemu: (31 commits) target/i386: Extract x86_cpu_exec_halt() from accel/tcg/ accel/tcg: Introduce TCGCPUOps::cpu_exec_halt() handler accel/tcg: Inline need_replay_interrupt target/i386: Extract x86_need_replay_interrupt() from accel/tcg/ accel/tcg: Introduce TCGCPUOps::need_replay_interrupt() handler accel/tcg: Use CPUState.cc instead of CPU_GET_CLASS in cpu-exec.c target/loongarch: Constify loongarch_tcg_ops include/qemu: Add TCGCPUOps typedef to typedefs.h accel/tcg: Un-inline icount_exit_request() for clarity accel/tcg: Rename tcg_cpus_exec() -> tcg_cpu_exec() accel/tcg: Rename tcg_cpus_destroy() -> tcg_cpu_destroy() accel/tcg: Rename tcg_ss[] -> tcg_specific_ss[] in meson accel/tcg: Move perf and debuginfo support to tcg/ accel/tcg: Remove #ifdef TARGET_I386 from perf.c tcg: Make tb_cflags() usable from target-agnostic code accel/tcg: Make use of qemu_target_page_mask() in perf.c target: Make qemu_target_page_mask() available for *-user accel/tcg/cpu-exec: Use RCU_READ_LOCK_GUARD tests/tcg: Add the PROT_NONE gdbstub test tests/tcg: Factor out gdbstub test functions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to '')
| -rw-r--r-- | include/exec/cpu-common.h | 69 |
1 files changed, 57 insertions, 12 deletions
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index fef3138d29..dcbd5f5783 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -3,9 +3,11 @@ /* CPU interfaces that are target independent. */ +#include "exec/vaddr.h" #ifndef CONFIG_USER_ONLY #include "exec/hwaddr.h" #endif +#include "hw/core/cpu.h" #define EXCP_INTERRUPT 0x10000 /* async interruption */ #define EXCP_HLT 0x10001 /* hlt instruction reached */ @@ -14,18 +16,6 @@ #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ -/** - * vaddr: - * Type wide enough to contain any #target_ulong virtual address. - */ -typedef uint64_t vaddr; -#define VADDR_PRId PRId64 -#define VADDR_PRIu PRIu64 -#define VADDR_PRIo PRIo64 -#define VADDR_PRIx PRIx64 -#define VADDR_PRIX PRIX64 -#define VADDR_MAX UINT64_MAX - void cpu_exec_init_all(void); void cpu_exec_step_atomic(CPUState *cpu); @@ -217,4 +207,59 @@ G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); G_NORETURN void cpu_loop_exit(CPUState *cpu); G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); +/* same as PROT_xxx */ +#define PAGE_READ 0x0001 +#define PAGE_WRITE 0x0002 +#define PAGE_EXEC 0x0004 +#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) +#define PAGE_VALID 0x0008 +/* + * Original state of the write flag (used when tracking self-modifying code) + */ +#define PAGE_WRITE_ORG 0x0010 +/* + * Invalidate the TLB entry immediately, helpful for s390x + * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() + */ +#define PAGE_WRITE_INV 0x0020 +/* For use with page_set_flags: page is being replaced; target_data cleared. */ +#define PAGE_RESET 0x0040 +/* For linux-user, indicates that the page is MAP_ANON. */ +#define PAGE_ANON 0x0080 + +/* Target-specific bits that will be used via page_get_flags(). */ +#define PAGE_TARGET_1 0x0200 +#define PAGE_TARGET_2 0x0400 + +/* + * For linux-user, indicates that the page is mapped with the same semantics + * in both guest and host. + */ +#define PAGE_PASSTHROUGH 0x0800 + +/* accel/tcg/cpu-exec.c */ +int cpu_exec(CPUState *cpu); + +/** + * env_archcpu(env) + * @env: The architecture environment + * + * Return the ArchCPU associated with the environment. + */ +static inline ArchCPU *env_archcpu(CPUArchState *env) +{ + return (void *)env - sizeof(CPUState); +} + +/** + * env_cpu(env) + * @env: The architecture environment + * + * Return the CPUState associated with the environment. + */ +static inline CPUState *env_cpu(CPUArchState *env) +{ + return (void *)env - sizeof(CPUState); +} + #endif /* CPU_COMMON_H */ |