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| author | Martin Kaiser <martin@kaiser.cx> | 2020-01-17 14:09:31 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-01-17 14:27:16 +0000 |
| commit | f03965490e4e4223903e79a4ec97139ccdd48e1b (patch) | |
| tree | 55142acbe23b9f4057732cd4cca267446bff56a8 /include/hw/arm/fsl-imx25.h | |
| parent | 21bf9b06cb6d07c6cc437dfd47b47b28c2bb79db (diff) | |
| download | focaccia-qemu-f03965490e4e4223903e79a4ec97139ccdd48e1b.tar.gz focaccia-qemu-f03965490e4e4223903e79a4ec97139ccdd48e1b.zip | |
i.MX: add an emulation for RNGC
Add an emulation for the RNGC random number generator and the compatible RNGB variant. These peripherals are included (at least) in imx25 and imx35 chipsets. The emulation supports the initial self test, reseeding the prng and reading random numbers. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/arm/fsl-imx25.h')
| -rw-r--r-- | include/hw/arm/fsl-imx25.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h index 241efb52ae..1c86bb55fb 100644 --- a/include/hw/arm/fsl-imx25.h +++ b/include/hw/arm/fsl-imx25.h @@ -24,6 +24,7 @@ #include "hw/timer/imx_gpt.h" #include "hw/timer/imx_epit.h" #include "hw/net/imx_fec.h" +#include "hw/misc/imx_rngc.h" #include "hw/i2c/imx_i2c.h" #include "hw/gpio/imx_gpio.h" #include "exec/memory.h" @@ -50,6 +51,7 @@ typedef struct FslIMX25State { IMXGPTState gpt[FSL_IMX25_NUM_GPTS]; IMXEPITState epit[FSL_IMX25_NUM_EPITS]; IMXFECState fec; + IMXRNGCState rngc; IMXI2CState i2c[FSL_IMX25_NUM_I2CS]; IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS]; MemoryRegion rom[2]; @@ -211,6 +213,8 @@ typedef struct FslIMX25State { #define FSL_IMX25_GPIO4_SIZE 0x4000 #define FSL_IMX25_GPIO3_ADDR 0x53FA4000 #define FSL_IMX25_GPIO3_SIZE 0x4000 +#define FSL_IMX25_RNGC_ADDR 0x53FB0000 +#define FSL_IMX25_RNGC_SIZE 0x4000 #define FSL_IMX25_GPIO1_ADDR 0x53FCC000 #define FSL_IMX25_GPIO1_SIZE 0x4000 #define FSL_IMX25_GPIO2_ADDR 0x53FD0000 @@ -238,6 +242,7 @@ typedef struct FslIMX25State { #define FSL_IMX25_EPIT1_IRQ 28 #define FSL_IMX25_EPIT2_IRQ 27 #define FSL_IMX25_FEC_IRQ 57 +#define FSL_IMX25_RNGC_IRQ 22 #define FSL_IMX25_I2C1_IRQ 3 #define FSL_IMX25_I2C2_IRQ 4 #define FSL_IMX25_I2C3_IRQ 10 |