diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-05-17 12:51:36 +0200 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-05-26 15:33:59 -0700 |
| commit | faf39e828374d83ca82b02c0c25cdeca9ce9581e (patch) | |
| tree | 4ea45fae01845a3c21c581aaa0ff62e95ea276f8 /include/hw/core/cpu.h | |
| parent | 715e3c1afb0022fb2e0f60a198ed2c740e3c48f4 (diff) | |
| download | focaccia-qemu-faf39e828374d83ca82b02c0c25cdeca9ce9581e.tar.gz focaccia-qemu-faf39e828374d83ca82b02c0c25cdeca9ce9581e.zip | |
cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210517105140.1062037-20-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include/hw/core/cpu.h')
| -rw-r--r-- | include/hw/core/cpu.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 15b16d3f6d..af6246c905 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -109,8 +109,6 @@ struct SysemuCPUOps; * associated memory transaction attributes to use for the access. * CPUs which use memory transaction attributes should implement this * instead of get_phys_page_debug. - * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for - * a memory access with the specified memory transaction attributes. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @gdb_num_core_regs: Number of core registers accessible to GDB. @@ -152,7 +150,6 @@ struct CPUClass { hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); - int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); |